This application claims the priority from Korean Patent Application No. 2003-04578 filed on Jan. 23, 2003, incorporated herein by reference.
1. Field of the Invention
The present invention relates to a synchronous semiconductor device and, more particularly, to a circuit for generating a data strobe signal used in a double data rate (DDR) synchronous semiconductor device.
2. Description of the Related Art
A synchronous semiconductor device, such as a DDR memory device, outputs data in synchronization with a data strobe signal. FIG. 1 is a timing diagram of signals associated with a typical synchronous semiconductor device. Referring to FIG. 1, the semiconductor device receives an active command ACT or a read command RD synchronized with a clock signal CLK. Responsive to, e.g., the read command RD, the semiconductor device outputs data DOUT after a predetermined number of clock cycles. For a single data input/output pin, data bits e.g., A1-A4 and B1-B4, are each sequentially output responsive to the single read command RD.
When it outputs data, the semiconductor device provides a gate strobe signal DQS. The gate strobe signal DQS enables another device, such as a memory controller, to easily receive the output data DOUT. As shown in FIG. 1, the data strobe signal DQS is in a state of high impedance (Hi-Z) when the device does not output data. The data strobe signal is in an active state (i.e., toggles synchronous to the clock signal CLK) when the device outputs data DOUT. In an active state, the data strobe signal DQS includes a preamble period and postamble periods.
FIG. 2 is a data output circuit of a conventional synchronous semiconductor device. Referring to FIG. 2, the data output circuit is a wave-pipeline-type data output circuit. As the operating speed of semiconductor devices increases, CAS latency also increases. In high-speed semiconductor devices, wave-pipeline-type data output circuits are widely used to embody long CAS latencies of 5-6 or more.
Data is output from a memory cell array 100 to a corresponding array of latches 111-122. The data stored in the latches 111-122 is output to the next latch 130 responsive to pipeline control signals (CDQF1-CDQF6, CDQS1-CDQS6). The data DO stored in the latch 130 is output via a tri-state control circuit 140 to an output data buffer 150.
The tri-state control circuit 140 outputs pull up data DOP and pull down data DON to the output data buffer 150, responsive to the data DO and a tri-state control signal PTRSTDS.
The output data buffer 150 includes a pull up transistor TP1 and a pull down transistor TN1. The pull up transistor TP1 and the pull down transistor TN1 drive the output data DOUT to a supply voltage VDD or a ground voltage level responsive to the pull up data DOP and the pull down data DON, respectively.
When the tri-state control signal PTRSTDS is at a low level, the pull up data DOP is at a low level and the pull down data DON is at a high level, irrespective of data DO. Accordingly, both the pull up transistor TP1 and the pull down transistor TN1 of the output data buffer 150 are turned off, putting the output data DOUT in a Hi-Z or tri-state.
On the other hand, when the tri-state control signal PTRSTDS is at a high level, the pull up data DOP and the pull down data DON are both at a high or a low levels according to the logic level of the data DO. Accordingly, only one of the pull up transistor TP1 and the pull down transistor TN1 of the output data buffer 150 is turned on to provide data DOUT.
FIG. 3 is a circuit for generating a data strobe signal of a conventional synchronous semiconductor device. Referring to FIG. 3, the conventional circuit for generating a data strobe signal is similar to the data output circuit of FIG. 2.
A high-level signal H or a low-level signal L is input to a latch 230 responsive to one of the pipeline control signals CDQF1-CDQF6 and CDQS1-CDQS6 or a preamble signal CDQPRE. Data DS stored in the latch 230 is output via the tri-state control circuit 240 to a data strobe buffer 250. The preamble signal CDQPRE is a signal for generating a low-level preamble period. Since the pipeline control signals CDQF1-CDQF6 and CDQS1-CDQS6 are activate in order, that is CDQF1, CDQS1, CDQF2, CDQS2, . . . , CDQF6, and CDQS6, the high-level signal H and the low-level signal L are alternately input to the latch 230.
The tri-state control circuit 240 outputs a pull up control signal DSP and a pull down control signal DSN to the data strobe buffer 250 responsive to the data DS and the tri-state control signal PTRSTDS.
The data strobe buffer 250 includes a pull up transistor TP2 and a pull down transistor TN2. The pull up transistor TP2 and the pull down transistor TN2 generate a data strobe signal DQS responsive to the pull up control signal DSP and the pull down control signal DSN, respectively.
When the tri-state control signal PTRSTDS is at a low level, the pull up control signal DSP is at a low level and the pull down control signal DSN is at a high level, irrespective of the data DS stored in the latch 230. Accordingly, both the pull up transistor TP2 and the pull down transistor TN2 of the data strobe buffer 250 are turned off, putting the data strobe signal DQS in a Hi-Z state.
On the other hand, when the tri-state control signal PTRSTDS is at a high level, the pull up control signal DSP and the pull down control signal DSN are both at a high level or a low level according to the logic level of the data DS. Accordingly, only one of the pull up transistor TP2 and the pull down transistor TN2 of the data strobe buffer 250 is turned on. As a result, the data strobe signal DQS is at a high level or a low level. That is, when the tri-state control signal PTRSTDS is at a high level, the low-level signal H is latched by CDQPRE to generate the preamble of a strobe signal. Also, the high-level signal H and the low-level signal L are alternately latched by CDQPRE and pipeline control signals CDQF1-CDQF6 and CDQS1-CDQS6 to generate a toggling data strobe signal DQS. Once the tri-state control signal PTRSTDS returns to a low level, a postamble is generated and the data strobe signal returns to a Hi-Z state.
In the conventional circuit for generating a data strobe signal, the tri-state control signal PTRSTDS cannot be precisely synchronized with the data strobe signal DQS. That is, the tri-state control signal PTRSTDS must be synchronized with the data strobe signal DQS at the same time as valid data DS is latched in the latch 230, and then be activated to a high level. If the tri-state control signal PTRSTDS is at a high level before the valid data DS is latched in the latch 230, however, an invalid strobe signal DQS may be generated. Or, if the tri-state control signal PTRSTDS is at a high level after the valid data DS is latched in the latch 230, the preamble period may be shortened.
In the conventional data output circuit as shown in FIG. 2, as the CAS latency increases, the number of latches 111-122 and pipeline control signals CDQFi, CDQSi, i=1-6 increases. Accordingly, the size of the data output circuit also increases. Likewise, the circuit for generating a data strobe signal is larger with increasing CAS latency.